The present invention generally relates to data processing systems and more particularly to clock systems utilized in controlling the transfer of information in such data processing systems.
In data processing systems, the transfer of information is typically controlled by clock pulses derived from clock cycles generated by a clock system. In a typical clock system, the clock generates a rectangular wave train signal, with the signal being a high state for a portion of the clock cycle and the signal being in a low state for the remainder of the clock cycle. In this type of clock system, the clock pulses are generated by detecting the change of signal from the high to low state and/or from the low to high state.
The period of the clock cycle of a data processing system is usually chosen to match the speed of the central processor to the speed of the memory. It is not unusual for vendors of data processing systems to offer a selection of memories having different speeds to be used in conjunction with a given central processor model. In these cases, the availability of a clock system with a selectable clock cycle period will allow easy matching of the central processor speed to that of the memory chosen.
In microprogrammed data processing systems, the execution time of the various microoperations will usually vary in accordance with the complexity of the microoperation performed. The more complex operations usually requiring more time to allow the signals more time to propagate through the increased number of logic gates involved. To maximize performance of a microprogrammed data processing system, it is desirable to have a clock cycle period available that matches the time required by each distinct microoperation. Although this matching could be accomplished by having multiple clock systems, it is much more desirable of circuit component expense and synchronization problems, to have one system from which a variety of predetermined clock cycle periods can be dynamically selected. The selection process should be such that after the microinstruction is read from the microprogram control store, and the particular microoperation to be performed by the microinstruction is determined, the clock cycle period can be adjusted to permit sufficient time, but not excessive time, to complete the particular mircooperation in the process of being executed. The clock cycle period can be implicitly selected by being associated with the microoperation of the microinstruction with the microoperation decoder providing one or more bits used to select the clock cycle period. In a data processing system that does not overlap the execution of microinstructions, e.g., the next microinstruction being read during the execution of the current microinstruction, it is important that the clock system be such that the clock cycle period selection and generation be done within the selected clock cycle period.
In any clock system, particularly when used in a data processing system, the stability of the clock cycle period is important. That is, it is desirable that the clock cycle period vary as little as possible due to variation in component operating temperature, operating voltage, or the particular component used in fabrication of a particular clock system. Each component used in fabricating a clock system has its own propagation time tolerances. Because the summation of the individual propagation time tolerances of each component used in a path of a clock system circuit is used to determine the worst case timing of a clock system, it follows that reducing the number of components in each path will lead to increased clock stability. Stability can also be increased by choosing components which inherently have narrower tolerances than other components. For example, it may be desirable in a clock system circuit to use a delay line which has a typical propagation time tolerance of plus or minus 5% due to voltage and temperature variations rather than multivibrators or one shots which have looser typical propagation time tolerances. By minimizing the number of components and by using components with inherently narrower tolerances, manufacturing economy can be achieved and the need to individually tune each clock system during manufacture can be eliminated.
A clock system in a data processing system is generally inhibited from generating clock pulse when information is not to be strobed into a receiving element, so as to prevent the transfer of erroneous information or loss of information thereby creating an error condition. Accordingly, a stall signal or condition is generated. A typical example of a stall condition may be, for example, that condition under which a utilizing element, such as a central processor, is waiting for the data processing system's memory to provide information thereto. When the receiving element is expecting the information from the memory, a clock pulse is not generated for strobing the information to the receiving element, particularly if there is an indication that the memory will not be providing such information for possibly another clock cycle. Accordingly, a stall condition is generated that will stall the clock by preventing the clock rectangular wave train signal from changing state, thereby stalling the generation of further clock pulses. By providing a stall high signal that stalls the clock rectangular wave train signal in the high state, the high to low clock pulse can be inhibited. By providing a stall low signal that stalls the clock rectangular wave train signal in the low state, the low to high clock pulse can be inhibited. These stall conditions however, upon an indication that the information will be presently transferred, will be cleared so as to generate another clock cycle and the pulses derived therefrom. It is important in such clock systems that the clock be able to start up again in a minimum period of time after the removal of the stall condition. An example of a stallable clock system is given in U.S. Pat. No. 4,134,073 "Clock System Having Adaptive Synchronization Feature" issued to William W. MacGregor and assigned to the assignee of the present invention.